High Level Synthesis CAD Electronics

High Level Synthesis

High Level Synthesis (or Behavioural Synthesis) is automatic compilation (translation) from a description which is relatively easy to write and read to a representation that can be automatically implemented. The most common synthesis today compiles from a register transfer level language (RTL) to a netlist of existing design fragments (cells, gates, CLBs) in an ASIC/FPGA technology. High Level Synthesis is distinguished from RTL Synthesis by starting from a more abstract description, which takes less effort to write and is easier to read and understand. Thus the High Level Synthesis tool takes over more of the design work.

• - Includes the infrastructure needed to build a HLS system including documentation, publications and tools. The commercial usage of the New Eindhoven Architectural Synthesis Toolkit sources and documentation are owned by a corporation. From Eindhoven Univer
  
• - Synthesis and Partitioning for Adaptive and Reconfigurable Computer Systems is an integrated design system for automatically partitioning and synthesizing designs for reconfigurable boards with multiple field-programmable devices (FPGAs). Includes overvie
  
• - Conducts design and design automation research projects including high level synthesis, reconfigurable designs and architectures and system modelling. Includes project descriptions, papers and tools. From University of California, Irvine.
  
• - Vendor description of an application-specific, high-level behavioral synthesis tool to assist in the development of SoC products.
  
• - Comprehensive list of links to information about commercial HLS tools.
  
• - Well known researcher.
  
  

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